module cbd_core(
	input				enable,
	input				model,//0->4 1->6
	input		[5:0]	data_in6,
	input		[3:0]	data_in4,
	output	reg	[11:0]	data_out
	);

	wire	[5:0]	data_in;
	wire	[2:0]	data_out_temp;

	assign	data_in =	enable ? model ? data_in6 : {1'b0,data_in4[3:2],1'b0,data_in4[1:0]} : 6'b0;

	assign	data_out_temp = data_in[0] + data_in[1] + data_in[2] - data_in[3] - data_in[4] - data_in[5];

	always@(data_out_temp)
	begin
		case (data_out_temp)
			3'b000:	data_out <= 12'd0;
			3'b001:	data_out <= 12'd1;
			3'b010:	data_out <= 12'd2;
			3'b011:	data_out <= 12'd3;
			// 3'd100:	data_out <= 12'd2;
			3'b101:	data_out <= 12'd3326;
			3'b110:	data_out <= 12'd3327;
			3'b111:	data_out <= 12'd3328;
			default:data_out <= 12'd0;
		endcase
	end


endmodule